This invention relates to a semiconductor integrated circuit such as a semiconductor memory device, etc. and in particular to a semiconductor integrated circuit, with an improved circuit operation speed, and improved stabilization of the operation and with improved reliability such as the immunity or strength against latch-up, etc.
Memory devices, which combine MOS transistors, whose electric power consumption is small, with bipolar transistors capable of high speed operation in order to make the most of the advantages of both kinds of transistors, have been developed.
FIG. 3 is a block diagram illustrating the construction of a memory combining MOS transistors with bipolar transistors, which was studied by the inventors of this invention before the application thereof. Such a memory is provided with a function to read out information stored in memory cells, as well as to write information in memory cells in accordance with input signals. That is, as indicated in FIG. 3, the input signal received is amplified by an input buffer and decoded by a decoder. Then the signal selects a word line and a driving circuit not shown in the figure drives a Y-switch so as to select one of data lines. In this way information read out from a memory cell is amplified by a sense amplifier through a data line and a pair of common data line and outputted to a data output terminal through an output buffer. The access time representing this memory speed is, as indicated in FIG. 4, 3 ns for the input buffer, 4 ns for the decoder, 4 ns for the sense amplifier, and 2.5 ns for the output buffer. That is, in the access time of 13 ns, the delay times necessary for these circuits are nearly equal to each other and therefore, in order to increase the speed, it is necessary to shorten the delay time for each of these circuits. Further, the point to which attention should be paid, when the circuit stabilization of the operation is improved, consists the desirability to suppress to the utmost the increase in the chip size of the memory LSI. Since the ratio of the area occupied by each of these circuits in the memory area is determined, as indicated in FIG. 4, the measure of the chip size of the memory LSI is determined on the basis thereof. As clearly seen from this figure, if attention is paid to the increase in the size of memory cells, the increase in the occupation area of the other circuits does almost not contribute to the chip size.
On the other hand, recent electronics have been directed towards a higher speed and with more functions, not excepting the memory LSI and it is desired to increase further the speed and the degree of integration and to lower electric power consumption.
In a prior art semiconductor memory device, it was limited to increasing the speed, because it had the following properties, and the access time was almost as indicated in FIG. 4 for a memory designed with the minimum working size of 2 .mu.m.
(a) an MDS type current mirror circuit is used in the input buffer circuit;
(b) a successive decoding circuit is used in the decoder circuit;
(c) MOS transistors are used for data line load elements; and
(d) the electrostatic capacitance of the common data line sending signals to the sense amplifier is high.
Because of these factors that are characteristic of the prior art circuit, it was difficult to increase further the memory operation speed.
Further, as another prior art semiconductor device, there is known a device disclosed e.g. in Japanese Patent Unexamined Publication No. 60-217725, in which a resistor or a constant current source is used as a bias current source for an emitter follower circuit.
Still further, heretofore, in order to lower electric power consumption, which increases with and increasing degree of integration of the LSI, it has also been tried to form the LSI by using CMOSs. However, in the case where low electric power consumption and a high speed operation are required, recently BiCMOS.LSIs, in which bipolar transistors and MOS transistors are integrated in the same chip, are studied. In these LSIs the amplitude of signals in their inner circuits is about 5 V. Contrarily thereto, the amplitude of the input signal to the LSIs is about 0.8 V for ECLs seeking for high speed characteristics and 1.4 V at the lowest for TTLs used usually in CMOS.LSIs, these values being small with respect to 5 V stated above, and therefore it is necessary to convert the signal level at the input part of the LSIs. Further, in a memory LSI, it is necessary to implify the amplitude of the signal read out from a memory cell, to a desired level. As a circuit for converting signals at the ECL level (-0.9 V--1.7 V) into those at the level (0 V--5 V) used in CMOS circuits etc., there is known a circuit combining a CMOS differential amplifier circuit, a level shift circuit and a current mirror type buffer circuit, discussed e.g. in ISSC Digest of Technical Papers, 1982, pp. 248-249. Although this circuit is constructed only by MOS transistors and therefore its construction is simple, is a result of a large number of circuit stages used, the time necessary for the conversion is longer than 4 ns and it is not possible to achieve high speed characteristics. Furthermore electric current consumed by fifteen of these circuits is 65% of the total consumed current of 150 mA of an LSI.